学术讲座：

1、Electromobility research in Singapore BY Prof. Douglas L. Maskell (Nanyang Technological University, Singapore )

2、A Routing Architecture for FPGAs with Dual-VT Switch Boxes and Logic Clusters BY Prof. Ha Yajun (National University of Singapore )

主持人：李仁发

地点：基地第一会议室

时间：6月5日上午 9:30 -11:30   内容：集群架构的FPGA

          下午 2:30 - 4:30   内容：新加坡电动汽车的研究发展

1、Electromobility research in Singapore

Abstract

The TUM CREATE centre for electromobility is a major research initiative sponsored by the National Research Foundation (NRF) of Singapore. Multidisciplinary research is structured across four clusters: Electrical Energy storage; Simulation, computation and communication; electric vehicles; and Infrastructure and transportation, and is jointly performed by professors from TechnischeUniversitätMünchen (TUM) and Nanyang Technological University (NTU). The aim is the development of innovative technologies and future transportation concepts matching the challenging requirements of fast growing and continuously changing tropical megacities. The individual projects and work packages are developed and performed in close collaboration with many industry partners, most of which are located in Singapore.

This presentation will give an overview of the project before focusing on the activities of the Simulation, computation and communication cluster.

2、A Routing Architecture for FPGAs with Dual-VT Switch Boxes and Logic Clusters

Abstract

Low energy consumptions are generally needed if FPGAs are going to be used in mobile products. In this talk, we present a novel routing architecture for FPGAs with dual-VT LUT and switch box architectures. The use of reverse back bias (RBB) is one strategy for mitigating leakage power, a critical issue as process technologies shrink relentlessly towards sub-nano proportions. FPGAs with the ability to adjust fabric threshold voltage Vt at the configuration time offer leakage power reduction without sacrificing circuit speed. Most of the related works today investigate dual-VT optimizations at the logic cluster level; Altera’s Stratix-III/IV line of FPGAs already demonstrates the feasibility of a similar architecture. We present a further advancement to the dual-VT architecture - the switch box, and a routing architecture that demonstrates the effectiveness of this true dual-VT fabric architecture. Our switch box advancement alone yields an average of 17.44% in leakage power savings, and with the full EDA flow an average 29.65% in total power savings is observed.

Short Bio of Prof. Douglas L. Maskell

 My main research focus is in the area of embedded systems. I examine research problems that aim to overcome the emerging challenges posed by hybrid computing systems, particularly those introduced by the trend to incorporate reconfigurable fabrics into embedded and performance computers so as to significantly improve the overall performance of the computing system. This effort involves the development of tools, algorithms & architectures and system level modelling, simulation & design to improve the performance & management of the computing resources. I am a member of the Centre for High Performance Embedded Systems (CHiPES) at NTU, where I head the Reconfigurable Computing group.

I also conduct research into the deployment of embedded systems technology to various applications, including: efficient digital filters and fuzzy-neuro controllers. Architectures with low complexity, for embedded applications, such as the use of fuzzy-neuro controllers for the regulation of insulin in the treatment of diabetes, are being developed (with KK Hospital). I have a passion for the environment and for using renewable energy and have applied my modelling and simulation expertise to projects in this exciting field. These have included solar energy systems a major EV related initiative: the NRF TUM-CREATE Electromobility in Megacities project.

Selected Publications:

1. Yongchao Liu, Bertil Schmidt, Douglas L. Maskell: "CUSHAW: a CUDA compatible short read aligner tolarge genomes based on the Burrows-Wheeler transform", accepted, Bioinformatics, 2012.

2. J.C. Patra and D.L. Maskell, “Modeling of Multi-Junction Solar cells for Estimation of EQE under Influence of Charged Particles Using Artificial Neural Networks”, in press, Renewable Energy, 2012.

3. J. Cui and D.L. Maskell, “A Fast High-level Event-driven Thermal Estimator for Dynamic Thermal Aware Scheduling”, accepted, IEEE Trans. Computer-Aided Design Integr. Circuits Syst., 2012.

4. Y. Liu, B. Schmidt and D. L. Maskell, “Parallelized short read assembly of large genomes using de Bruijn graphs”, BMC Bioinformatics, vol. 12:354, 2011.

5. Y. Liu, B. Schmidt and D.L. Maskell, “DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI”, BMC Bioinformatics, vol. 12:85, 2011.

Short Bio of Prof. Ha Yajun

Dr. Yajun Ha received the B.S. degree in Electrical Engineering from Zhejiang University, China, in 1996, the M.Eng. degree in Electrical Engineering from National University of Singapore, in 1999, and the Ph.D. degree in Electrical Engineering from KatholiekeUniversiteit Leuven (KULeuven), Belgium in February 2004.

From 1996 to 1997, he was a Research Engineer in the Shanghai Aerospace Bureau, Shanghai, China. From January 1999 to February 2004, he worked as a researcher at the Inter-UniversityMicroElectronicsCenter (IMEC) in Leuven, Belgium. Since February 2004, he has been with the Dept. of Electrical and Computer Engineering at National University of Singapore, where he is currently an Assistant Professor.

His research interests are in the general area of embedded computing (VLSI) architecture and design methodologies, with the focus on reconfigurable computing. He has published around 60 internationally peer-reviewed journal/conference papers on these topics.

He has served a number of positions in the professional communities. He serves as the Associate Editor for the IEEE Transactions on Circuits & Systems II (2011-2013) and the Journal of Low Power Electronics (Since 2009). He serves as the General Co-Chair of ASP-DAC 2014; Program Co-Chair for FPT 2010; Chair of the Singapore Chapter of the IEEE Circuits and Systems (CAS) Society (2011 and 2012); Member of ASP-DAC Steering Committee; Member of IEEE CAS VLSI and Applications Technical Committee. He is the Program Committee Member for a number of well-known conferences in the fields of embedded systems and FPGAs, such as DATE, ASP-DAC, FPL, FPT, RAW, ARC and ERSA. He served as an external proposal reviewer for the Netherlands Science Foundation (2007) and the Qatar National Research Fund (2009, 2012). He was an Expert Group Member of Chinese National Electronic Design Contest (NUEDC) - Embedded System Design Invitational Contest (2006, 2008 and 2010). He is currently a Senior Member of IEEE.

Selected Publications:

1. A. Kumar, B. Mesman, H. Corporaal and Y. Ha, "Iterative Probabilistic Performance Prediction for Multi-Application Multi-Processor Systems", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol 29, Issue 4, pp538-551, Apr 2010.

    

2. Y. Pu, J. Pineda, H. Corporaal and Y. Ha, “An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65nm CMOS with Sub/Near Threshold Supply Voltage”, IEEE Journal of Solid-State Circuits, Vol 45, Number 3, pp. 668-680, Mar 2010.

    

3. H. Tian, S. Fernando, H. Soon, Q. Zhang, C. Zhang, Y. Ha and N. Chen, "Ultra Storage Efficient Time Digitizer for Pseudo Random Single Photon Counter Implemented on Field Programmable Gate Array", IEEE Trans. on Biomedical Circuits and Systems, Vol 4, Issue 1, pp. 1-10, Feb 2010.

    

4. A. Kumar, S. Fernando, Y. Ha, B. Mesman and H. Corporaal, "Multi-processor Systems Synthesis for Multiple Use-Cases of Multiple Applications on FPGA", ACM Transactions on Design Automation of Electronic Systems, Vol 13, Issue 3, July 2008, pp. 1-27, ISSN:1084-4309.