摘  要

        可重构计算具有软件编程的灵活性和硬件实现的高效性，是未来处理高密度计算的软件和硬件的平衡方案。高清视频标准H.264相对其他视频标准有更高的压缩效率和更好的视频质量。

        但是由于H.264的高压缩率需要超大数据计算量，普通的微机很难完成复杂计算，而专用硬件的代价偏高。本文对过程级可重构计算进行了研究，并使用该方案对H.264视频标准进行了研究。本文主要工作如下为此进行了以下工作：

        首先，对过程级动态可重构进行了研究，从编程模型的角度出发，给出过程级软硬件协同设计的流程，明确设计中对目标应用的描述、综合、运行环境三个阶段应该完成的任务。

        其次，对H.264标准进行了模块划分，对各个模块进行了分析，重点对去块滤波器进行了研究。去块滤波模块主要是去除由于编码压缩中变换量化存在误差而产生的块现象，提高视觉效果。研究工作包括对去块滤波器的基于宏块处理的处理顺序的改进，对去块滤波的流水结构设计，以及为实现方案设计了恰当的RAM减少去块滤波的中间数据和对强滤波的数据通路进行了优化。

        然后，对去块滤波器设计的理论分析，使用硬件描述语言实现了去块滤波的设计方案，使用可重构设计的仿真平台进行仿真，验证了功能的正确性，使用综合工具，验证了设计的可行性和优越性。

        最后，为了使设计实现能够实现软件函数一样的通用性，本文将设计实现定制为IP核，供其他开发人员进行开发。

关键字：可重构计算；H.264；去块滤波；高清视频；IP核

Abstract

        For the combination of software programming flexibility and hardware efficiency, reconfigurable computing is a balance between software and hardware for intensive computing. H.264, a High Definition Television standard, has much better compressibility and definition, compared to other High definition Television standards.

        Nevertheless, its high compressibility is at the cost of large-scale computing, which can be hardly supported by general computers and is too costly to specific hardware. This paper has done some research into Procedure Level reconfigurable computing, which is used in H.264 video standard. The main works for the paper as follows:

        To begin with, Procedure-level dynamic reconfigurable computing is studied, and Procedure-level hardware/software co-design processes are presented from the view of programming model. The works should be finished at the stage of description, and synthesis and executing environment are proposed.

        Additionally, the H.264 codec is partitioned into sub-modules and all of them are investigated. Deblocking filter, the main module to decrease the video effectiveness, is the primary researching object. A new filter sequence based-on block is put forward, a pipeline design is given, and suitable RAMs are designed to cut down the intermediate data, data path for strong filter are optimized.

        Then, the deblocking filter design is analyzed theoretically, and realized in hardware description language Verilog. Simulations are carried out by Modelsim platform to verify the functions. The result of synthesis proved the design is viable and superior.

        At last, the design is packaged into IP core, which can be used by other people.

Key Word: Reconfigurable computing; H.264; deblocking filter; High Definition Television; IP core

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