讲座主题：Can We Fully Parallelize Loops? Hide Memory Latencies?
主讲人：沙行勉教授
Department of Computer Science University of Texas at Dallas
讲座时间：6月2日上午9：00-11：30
讲座地点：复临舍报告厅
Abstract:
With the advance of system level integration and system-on-chip, the high-tech industry is now moving toward parallel embedded systems such as VLIW, multi-core, and multi-processor systems. For example, Intel is developing 80-core CPU. But the software is far lagged behind. Software does not know how to efficiently use those resources. As loops are the most time-and-memory critical parts, we will show how to parallelize loops optimally based on our technique called "Multi-Dimensional (MD) Retiming". Though MD retiming can minimize the computation schedule, the relatively slow memory may still hinder the overall performance. A complete solution to hide memory latencies, which combines the MD retiming with prefetching and loop partitioning will also be presented. Many of our techniques give the best known results available in literatures.
本讲座也会讨论如何作研究，写文章，如何将研究成果在好的SCI国际期刊上发表。
Dr. Edwin Sha received the Master and Ph.D. degree from the Department of Computer Science, Princeton University, USA in 1991 and 1992, respectively. From August 1992 to August 2000, he was a faculty member in the Department of Computer Science and Engineering at University of Notre Dame, USA, and served as the Associate Chair since 1995. Since 2000, he has been a tenured full professor in the Department of Computer Science at the University of Texas at Dallas (UTD). After serving as the Computer Science Division Head at UTD, he has been the leader of the computer systems group and a leading professor of the computer engineering program at UTD.
He has published more than 250 research papers including more than 70 journal articles with more than 30 IEEE/ACM Transactions papers. He has been serving as editors for many premier journals including several IEEE Transactions, and as program committee members and Chairs in numerous international conferences.
